Rung 2 · in this browser

Every switch of every chip,
as wide as your GPU.

The recognised switch network of the 6502, compiled into code by v6502-compiled's own build and emitted a second time as WGSL, runs here on this device's GPU through WebGPU: the same kernel the native harness holds bit-exact against the CPU rung, lane for lane. Each cell below is one transistor-level chip's screen page. One machine is booted honestly at the switches (the wasm chip in this page, running the painter program assembled from the source further down), and that machine value crosses onto the GPU rung the way the crossing test proves it crosses: at the four planes, then wide.

starting

machine 0 · click a cell to focus it

0 machines on no adapter yet
0 aggregate · 0
sparse memory: 0 of the copy-on-write pool

The clock here is the count

Rung 2 is a throughput engine, and this page does not pretend otherwise: one sweep of the GPU advances every machine one half-cycle, so each chip runs at a few hundred half-cycles a second while the wall as a whole runs millions. The native measurement on one RTX 3070 is 4.95 million machine-half-cycles a second at 128,000 machines; what this device does is printed live above. A single chip in real time is a different rung's job: the games console runs rung 3 at 0.86 milliseconds a frame.

What each cell shows

The 256 bytes of the machine's screen page, one pixel per byte, colored by value. Every chip runs the same program; the byte at $FF, poked per lane before the first half-cycle through the kernel's copy-on-write memory, is the LFSR tap set that makes every chip a different run. Moving the pointer across the wall broadcasts a brush byte to $FE and every lane hears it at once. The pool readout above is the sparse memory doing its work: pages exist only where a lane has written.

The program, as source


    

Assembled in this page by the same assembler the programs page uses, booted once on the switch-level chip, then run wide. A browser without WebGPU, an adapter whose limits cannot hold the kernel's workgroup planes, or a spent page pool each stop the wall with the reason named, because a wall that silently showed wrong memory would be worse than no wall.