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1 PLAYER GWME. The events file located the write: the byte sent to $2007 for that tile was $20, the letter W, where the ROM's string, read out of CHR-ROM through $2007 a moment earlier, carried $0A, the letter A. The pins walked it back: the byte came from an LDA ($00),Y whose pointer and index crossed a page, and the CPU read the un-carried address, $0300, and never did the fixed-up read at $0400 where the A had been stored. Five instructions reproduced it on the 6502 repository's own lockstep of the switch-level chip beside the fast rung: after INY, the fast rung chose its variant of the next instruction by asking Y as stored, one instruction stale, because the result of the increment was still in the ALU's hold register and lands one half-cycle later. The switch-level chip has no such question to ask; the carry falls out of the transistors with the right Y.

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Then the console, with its fast CPU corrected to poll a taken branch as the die does, jammed on this cartridge's menu: NMI off, the main loop waiting on a sprite-zero hit that never came. The die on that record agreed with it to the last half-cycle, which put the CPU beyond suspicion, and a dump of the work RAM against the bytes the record's DMA carried named the fault: the 2A03 rung's sprite DMA read through the held CPU's bus, whose memo answers the CPU's quiet re-asks, so a page the DMA had read before came back as it was then. A game that never reads its sprite buffer kept its first frame's sprites for good. Fixed, with a test of two DMAs on a bus, the title screen has Mario on the ground, and the small sprite the earlier three-way comparison saw on the underline, which neither eye had, is gone: it was this.

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The head waits for each line's answer before it sends the next, and checks that an AT's answer carries the latch and byte it sent. It did not always: on 2026-09-18 a hand's record of 125 AT lines, sent back to back, overran the UNO's 64-byte receive buffer, some lines came back # ?, others were taken with digits missing (AT 2219 00 as at 2210 00), and Mario ran the wrong way on the replay while every check stayed quiet. The head also drops its count of latches when it sees the bridge's # reset, so a WAIT n after a reset cannot be satisfied by the session before (the cold-boot "Start is ignored" finding of the same day was exactly that).

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It also produced the first finding, and it came from reading a reply rather than from a check. Step 0.3's STATUS line said latch 482 with nothing wired to the board at all. Timer1 is a hardware counter and asks no questions: its input pin was floating, and it took 3,647 latches in three seconds, about 1.2 kHz of noise. Nothing failed, and that is the point. B0's whole first gate is clocks per latch, AT n hh is keyed by latch index, and B3's replay is a latch index throughout. A run begun before the console was powered would have carried an index that meant nothing, and every number downstream of it would have looked like a finding about the part.

The fix is one word twice: the two console-side inputs are INPUT_PULLUP rather than INPUT. The console drives both lines hard when it is on, so a 30 kilohm internal pull-up costs it nothing, and when it is off or unplugged the pins now sit at a defined level instead of picking up the room. Measured before and after on the same board: 3,647 latches in three seconds, then 0 in ten.

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Counts, agreed by both real parsers: 16,758 transistors, 8,770 nodes (ids to 10,905), 858 names. The sketch's first number, 16,871, was a regex counting the 114 transistors Quietust left inside a block comment in transdefs.js; a second comment-aware regex said 16,757, fumbling one entry. halfphi and the reference JS engine itself agree on 16,758, and the counts test records the saga: instruments lie before the code does.

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The recovery decoded every capture as broadcast NTSC, and the NES is not broadcast NTSC. Its line is 227 and a third subcarrier cycles (2728 grid samples, not 2730), so the burst phase advances a third of a cycle per line where broadcast advances half, over 262 progressive lines anchored on vsync rows 245..=247. Decoded as broadcast, every line landed two grid samples further rotated than the last: a smooth hue roll down the whole frame, invisible on the mostly-monochrome menu screen and unmissable on World 1-1. The broadcast assumption also mismeasured the scope clock at -740 ppm (2 in 2730 is 733 ppm); under the NES profile the same records measure -7 to -19 ppm. recover_nes is the fix: NES geometry, the burst target derived from the encoder's own wave-8 square, levels in the transcribed table's ABSOLUTE volts so the recovered frame decodes with the oracle's own constants. Proven on a synthetic NES capture (chained origins 8, 0, 4 so the anchored frame is the origin-0 one): chroma pointwise within 0.006, band luma means within 0.005, and the broadcast recovery on the same capture is the built-in mutation, which must miss by 10x or refuse.

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A finding on the way there, withdrawn. Cold-powered by the relay, the part's menu seemed never to take Start (nine runs: one latch, two, a press at 400, a sixty-latch hold, two presses) while it took Select, and took Start after a second reset. The byte reached the console (the port's data line low in the fourth slot of the poll), the model took the press cold with its RAM filled ten ways, and the difference was put down to state a cold boot leaves. It was the head: its count of the bridge's latches survived the bridge's RESET, so a WAIT after a reset returned at once and the scope caught the menu before the press (from wait for latch to armed in those runs' logs is the three seconds the arm takes; in the one that "took", 12.8 s). With the count cleared on the bridge's acknowledgement, the press takes with no reset at all, with one and with three (runs 193915, 194105, 194257, the number of resets in that order), the poll at the title's lines 247 and 249. The account is in open-items.md. The menu's logic read from the model's record stands: a press that arms a mask and a release that fires the switch, Select another way.

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Back to back, both engines lose the first value and land the rest one entry early: that is the model's behaviour and it is what the standard world hit. With idle between the writes, the reference lands every byte as written and rung 0 lands data OR (v & 0xff), the byte ORed with the low byte of the VRAM address (21|11 = 31, 11|12 = 13, 01|13 = 13, 2a|14 = 3e; on the row above $20, 11|22 = 33, so the term is the address, not the palette index). That was an engine divergence, the family's second after the spr_d rail-conflict hold, and it was invisible to every node golden because none of them paces a palette write: P1's program writes its palette back to back, and P2's schedule paces only OAM. The harness is not the cause (the hold row above).

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