The chip atlas: an address for every part

Generated by tools/export-atlas-doc.py from web/{groups,graph,schematic,timing}.json. Nothing below is typed by hand. Regenerate after any change to the die data or to a derivation, and the document follows.

Every node, transistor and wire on this die gets exactly one address, and a prefix of an address is a valid way to name the set beneath it. The point is an IP address rather than a hostname: the front routes, the back identifies.

8365 addresses: 1547 nodes, 3510 transistors, 3308 wires. All unique, all parseable, checked by the generator before this file is written.

The rubric

<container> : <class> : <slot>

Parse from the right. The slot follows the last colon, the class the one before it, and the container is everything left over. A fixed field count does not work: container keys legitimately contain colons (alat:ADL/ABL), and a bundle names two of them (regs:a~sbus:sb).

Why the separator is a colon

Measured, not chosen. Across the die's 707 names the punctuation in use is # ( ) + - . / _; container keys add :. A colon appears in zero die names, and kind:id is already how this project spells a container everywhere else. . and / were both out: . is in 33 names and 14 keys, / in 47 and 5.

The three fields

The slot is the die's number, and that is the load-bearing decision

Every other field is a derivation, and derivations here move: the chip map has already changed which kind owns a contested node, and the interrupt walk has already changed its ownership rule. An address whose last field were derived would break on every such improvement.

The generator proves the property rather than asserting it. Reversing the kind ownership order re-owns 88 of 1547 nodes and moves 0 slots.

So a prefix is a claim that can be revised, and the slot is not. Strip an address to its last field and the part is still findable.

The class vocabulary is closed, and it is 34 tokens

NMOS has no AND gate and no OR gate. A pullup holds the output high and a pulldown network to ground beats it, so every static gate is an inverted sum of products: legs in parallel are the ORs, transistors in series are the ANDs. The leg profile is therefore a complete description of what the gate computes, not a label for it. aoi2.1 is NOT((A AND B) OR C).

The tail is long, and that is the die being irregular rather than the rule being loose: 17 of the 34 classes hold fewer than five gates each, 11 of those being AOI shapes that the ALU and the flag logic build once. The rest are dyn2, dyn6, dyn8, dyn9, inert, nor9.

Facts ride as tags, never as fields

An address needs exactly one discriminator and it must be immutable. Anything else true about a part is a tag: queryable, unordered, and free to change without moving anything.

sbus:sb:bus:#1188                  name=sb3  bit=3@sb  depth=6
regs:x.SBX:dyn3:#1186              name=dpc3_SBX  opens=8  precharged  phase=phi1  depth=5  also=sbus:off  also=dpc:phi1
regs:a:bus:#737                    name=a0  bit=0@a  depth=7
clock:gen:dyn5:#943                name=cclk  opens=243  precharged  depth=4

bit= uses the tracer's measured bus-stem rule (letters only, no not complement, bit 0 named, at least seven of bits 0..7), which lands on 24 stems. depth= is hops from the nearest pin. phase= is measured by running the chip. also= names a container that claims this node in the overlapping layer but lost it in the partition.

Where the names come from

Worth stating because none of it is ours, and the answer is three deep. The source is 6502_datapath.wiki in the preservation archive.

So half of a control-line name is a coordinate and half is a function. The prefix is a real ordering: sorting the lines by their dpc index sorts them left to right across the die, with six inversions in 43, all adjacent pairs. Two indices are negative, dpc-1_ADL/ABL and dpc-2_ADH/ABH, because the address latch loads sit left of where the datapath's numbering starts.

tools/check-dpc-vs-wiki.py re-asks the wiki's claims of the chip.

The entries

132 groups over 23 kinds, covering all 1547 nodes exactly once, plus 138 containers that overlap on purpose. n is the node count; a group with a . in its id is a child of the one above it.

regs: registers

flags: status flags

alat: address latches

dbus: data bus

irp: instruction register

sbus: special bus

sdp: store pipeline

rdy: ready logic

pcr: program counter

pipe: pipeline latches

sync: SYNC

clock: clock generator

intr: interrupts

branch: branch logic

decimal: decimal correction

alu: ALU

incr: PC incrementer

chain: timing chain

bus: internal bus

stage: decode terms

pins: pins

rest: rest of a block

logic: static logic

Containers that exist only in the overlapping layer

These claim no node in the partition, because everything in them is already owned by a derivation that is more specific. They are still the honest answer to "what is this node part of".

122 nodes are in more than one container, at most 5. That number is not a defect: a node in the decimal correction is also in an ALU slice, and saying only one of those is a consequence of a drawing needing disjoint boxes.

What the address cannot tell you

• Direction. A pass transistor conducts both ways, so topology alone cannot say which end is the source. Hanson's SOURCE/DEST names are the only record of it, and they are authored, not measured.
• Neighbourhood. depth= is hops from a pin, which is a distance, not a neighbourhood. "What is within two hops" is a query, not a coordinate.
• Which container is most interesting. The partition picks one owner so a box can be drawn. also= carries the rest.
• Anything about node 866. It classifies as inert and that is correct: it gates one transistor and nothing in the chip can drive it, so no run can ever observe it.